1. Field of the Invention
This invention relates to electronic memory devices, and more specifically, to a semiconductor memory having a plurality of output ports such that a plurality of words stored in the memory may be accessed simultaneously.
2. Description of the Prior Art
Random access memories, or RAM's, are well known in the prior art. A block diagram of one such prior art RAM is shown in FIG. 1. Random access memory 400 of FIG. 1 contains memory cells 00 through 07 in row R.sub.0, memory cells 10 through 17 in row R.sub.1, and similar memory cells in rows R.sub.2 through R.sub.31, with memory cells on row R.sub.31 being numbered 310 through 317. Each memory cell is capable of storing one binary digit ("bit") of information, as either a logical "1" ("high") or logical "0" ("low").
In the operation of the RAM 400 depicted in FIG. 1, the binary representation of the row which is to be accessed is comprised of five binary bits, there being 32 rows, R.sub.0 through R.sub.31. These five bits are carried to row decoder 401 through leads 402a-402e. Row decoder 401 then applies a logical high on the selected row, while maintaining logical lows on all remaining deselected rows. A logical low is also applied to terminal 600, which is connected to each column C.sub.0 -C.sub.7 through buffer amplifiers B.sub.0 -B.sub.7, respectively. Assuming row R.sub.0 is selected by row decoder 401, row R.sub.0 will be high and rows R.sub.1 through R.sub.31 will all be low. If memory cell 00 is programmed to contain a logical one, it will conduct, thus connecting column C.sub.0 to row R.sub.0. This causes row R.sub.0 to pull column C.sub.0 high. In a similar manner, if memory cell 01 is programmed to a logical zero, it will not conduct. Thus, column C.sub.1 is not connected to row R.sub.0, and column C.sub.1 remains low. Thus, with row R.sub.0 selected (high) and rows R.sub.1 through R.sub.31 deselected (low), the logical states on columns C.sub.0 -C.sub.7 will be indicative of the logical states of the bits stored in memory cells 00-07, respectively.
Each row of RAM 400 contains two four-bit words. For example, row R.sub.0 contains a first word consisting of bits 00 through 03, and a second word consisting of bits 04 through 07. The first columns from each word, C.sub.0 and C.sub.4, are connected to first word decoder 501 as shown. Similarly, the second columns from each word, C.sub.1 and C.sub.5, are connected to second word decoder 502. Similarly, C.sub.2 and C.sub.6 are connected to third word decoder 503 and C.sub.3 and C.sub.7 are connected to fourth word decoder 504. Word decoder input lead 512 is connected to each word decoder 501-504. By applying either a logical 0 or a logical 1 to word decoder input lead 512, either the first word of the selected row, as appears on columns C.sub.0 -C.sub.3, or the second word of the selected row, as appears on column C.sub.4 -C.sub.7, may be selected. The selected word appears at output port 525, consisting of output terminal 525a for the first bit, output terminal 525b for the second bit, output terminal 525c for the third bit and output terminal 525d for the fourth bit.
In many applications, a mathematical or logical operation is performed on two words, thus requiring access to both words simultaneously. One prior art method of doing this is simply to use two identical RAMs, as shown in FIG. 2a. The same information is stored in both RAMs by virtue of the fact that every word written into one RAM is also written into the other at the same location. When two words are to be accessed simultaneously and independently, one, say word A, is taken from RAM 1, and the second, word B, is taken from RAM 2. Such a technique requires two complete RAMs, each with its own address register, row decoder, and word or column decoders. With the binary representation of the address location of word A applied to address input port A.sub.1 of RAM 1, word A appears at output port O.sub.1 of RAM 1, and is applied to mathematical or logical operation circuit 17. Similarly, with the binary representation of the address location of word B applied to address input port A.sub.2 of RAM 2, word B appears on output port O.sub.2 of RAM 2, and is applied to mathematical or logical operation circuit 17. Circuit 17 is thus able to perform its operation on word A and word B, with the resultant appearing on output port R of circuit 17. Such a technique becomes rather expensive, and consumes a rather large amount of space when the RAMs used are of even moderate size, due to the complete duplication of base address registers, row decoders and word decoders required to operate both RAMs.
Another prior art method is to use two complete independent addressing systems within one RAM (e.g., the RAM contained in the AMD 2901, manufactured by Advanced Micro Devices). One way this can be implemented is shown in FIG. 2b. This is a 16 word by 4-bit RAM with 2 simultaneous independent outputs. Each bit position is provided with two 16 to 1 multiplexers; one controlled by the A-address lines (providing word A comprised of bits A.sub.0 -A.sub.3) and the other by the B-address lines (providing word B comprised of bits B.sub.0 -B.sub.2). Thus, two cells in each bit position can be simultaneously and independently specified and accessed. The disadvantage of this approach is the excessive amount of circuitry required for the addressing, hence it is limited to relatively small RAMs.
Another prior art method of obtaining access to two words simultaneously is to read a first word, store this first word in a buffer memory, and then access the first word stored in the buffer memory and a second word contained in the RAM, simultaneously. A block diagram showing a circuit using this prior art technique is shown in FIG. 3. A flow chart depicting the required steps for this type of operation is shown in FIG. 4. First it is required to apply to address input port A.sub.1 of RAM 1 the binary representation of the address location required to access a first desired word, word "A". Word A is then stored in buffer memory 2 for later use. Next it is required to apply to address input port A of RAM 1 the binary representation of the address location required to access the second desired word, called word "B". The mathematical or logical operation may then be performed by operation circuit 17 on word A, as accessed from buffer memory 2 and available on output port O.sub.2 of buffer memory 2, and word B, as accessed from RAM 1 and available on output port O.sub.1 of RAM 1. The result from the mathematical or logical operation, available on output port R of operation circuit 17, may then be used or stored in a memory location reserved for the resultant. One disadvantage with this technique is that a separate buffer memory is required. Another, more serious disadvantage with this technique, is that the RAM must be accessed two separate times in order to have simultaneous access to word A and word B. The accessing of word and storage of word A in the buffer memory requires a finite amount of time, and in most applications these steps are repeated a large number of times, wherein the sum of the time delays created by accessing word A and word B individually becomes very large, thus drastically reducing the speed at which the system operates.